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devices incorporated 1 lf48908 two dimensional convolver 1 2 3 4 5 6 7 8 9 10 11 08/9/2000Clds.48908-j video imaging products q q q q q 40 mhz data and computation rate q q q q q nine multiplier array with 8-bit data and 8-bit coefficient inputs q q q q q separate cascade input and output ports q q q q q on-board programmable row buffers q q q q q two coefficient mask registers q q q q q on-board 8-bit alu q q q q q twos complement or unsigned operands q q q q q replaces harris hsp48908 q q q q q decc smd no. 5962-93007 q q q q q package styles available: ? 84-pin plastic lcc, j-lead ? 100-pin plastic quad flatpack features description lf48908 two dimensional convolver devices incorporated the lf48908 is a high-speed two dimensional convolver that imple- ments a 3 x 3 kernel convolution at real-time video rates. programmable row buffers are located on-chip, eliminating the need for external data storage. each row buffer can store up to 1024 pixels. two internal register banks are provided allowing two separate sets of filter coefficients to be stored simultaneously. adaptive filter operations are possible when both register banks are used. an on-chip alu is provided, allowing real-time arithmetic and logical pixel point operations to be performed on the image data. the 3 x 3 convolver comprises nine 8 x 8-bit multipliers, various pipeline registers, and sum- mers. a complete sum-of-products operation is performed every clock cycle. the frame signal resets all data registers without affecting the control and coefficient registers. pixel and coefficient input data are both 8-bits and can be either signed or unsigned integers. image data should be in a raster scan non-interlaced format. the lf48908 can internally store images as wide as 1024 pixels for the 3 x 3 convolution. by using external row buffers and multiple lf48908s, longer pixel rows can be used and convolutions with larger kernel sizes can be performed. out- put data is 20-bits and this guarantees no overflow for kernel sizes up to 4 x 4. a separate cascade input is used as the data input for summing results from multiple lf48908s. it can also function as the data input path when external line buffers are used. f igure 1. lf48908 b lock d iagram din 7-0 cin 9-0 caso 7-0 a 2-0 ld cs casi 15-0 clk hold frame reset oe dout 19-0 16 3 8 8 20 8 ealu 3 x 3 convolver alu row buffers control logic
devices incorporated lf48908 two dimensional convolver 2 video imaging products 08/9/2000Clds.48908-j f igure 2. lf48908 f unctional b lock d iagram din 7-0 1-4 cin 9-0 2:1 2:1 row buffer row buffer caso 7-0 7-0 15-8 a 2-0 ld cs control logic casi 15-0 2:1 shift 0 clk hold frame reset oe dout 19-0 i h g f e d c b a alu register alu 20 20 16 3 8 8 10 20 8 8 8 8 7-0 ealu note: numbers in register indicate number of pipeline delays.
devices incorporated 3 lf48908 two dimensional convolver 1 2 3 4 5 6 7 8 9 10 11 08/9/2000Clds.48908-j video imaging products a 2-0 control logic address lines a 2-0 determines which control logic register will receive the cin 9-0 data. cs chip select when cs is low, data can be loaded into the control logic registers. when cs is high, data can not be loaded and the register contents will not be changed. ld load strobe if cs and ld are low, the data present on cin 9-0 will be latched into the control logic register addressed by a 2-0 on the rising edge of ld. functional description the lf48908, a two-dimensional convolver, executes convolutions using internal row buffers to reduce design complexity and board space require- ments. 8-bit image data, in raster scan, non-interlace format, is convolved with one of two internal, 3 x 3 user- programable filter kernels. two 1024 x 8- bit row buffers provide the data delay needed to perform two-dimensional convolutions on a single chip. the result output of 20-bits allows for word growth during the convolution operation. the input data path (din 7-0 ) provides access to an 8-bit alu. this allows point operations to be performed on the incoming data stream before reaching the row buffers and the convolver. the length of these buffers is programmable for use in various video formats without the need for additional external delay. this device is configured by loading the coefficent data (filter kernels) and row buffer length through the coefficent data path (cin 7-0 ). internal registers are addressed using the a 2-0 address lines. chip select (cs) and load strobe (ld) complete the configuration interface which may be controlled by standard microproces- sors without additional external logic. signal definitions power v cc and gnd +5 v power supply. all pins must be connected. clock clk master clock the rising edge of clk strobes all enabled registers except for the control logic registers. inputs din 7-0 pixel data input din 7-0 is the 8-bit registered pixel data input port. data is latched on the rising edge of clk. cin 9-0 coefficient and control logic register input cin 7-0 is used to load the coefficient registers or can be used to provide a second operand input to the alu. cin 8-0 is used to load the initializa- tion register. cin 9-0 is used to load the alu microcode and row buffer length registers. the control regis- ter address lines, a 2-0 , determine which register will receive the cin data. the cin data is loaded into the addressed register by using the cs and ld control inputs. casi 15-0 cascade input the cascade input is used when multiple lf48908s are cascaded together or when external row buffers are needed. this allows convolutions of larger kernels or longer row sizes. outputs dout 19-0 data output dout 19-0 is the 20-bit registered data output port. caso 7-0 cascade output the data presented on caso 7-0 is the internal alu output delayed by twice the programmed internal row buffer length. controls reset reset control when reset is low, all internal circuitry is reset, all outputs are forced low, all control logic registers are loaded with their default values (which is 0 for each one except the alu microcode register which has a default value of 0000011000), and all other internal registers are loaded with a 0. frame new frame input control when asserted, frame signals the start of a new frame. when frame is low, all internal circuitry is reset except for the alu microcode, row length, initialization, coefficient, and alu registers. ealu enable alu register input when high, data on cin 7-0 is latched into the alu register on the next rising edge of clk. when low, data on cin 7-0 will not be latched into the alu register and the register con- tents will not be changed. hold hold control the hold input is used to disable clk from all of the internal circuitry. hold is latched on the rising edge of clk and takes effect on the next rising edge of clk. when hold is high, clk will have no effect on the lf48908 and all internal data will remain unchanged. oe output enable when oe is low, dout 19-0 is enabled for output. when oe is high, dout 19-0 is placed in a high- impedance state.
devices incorporated lf48908 two dimensional convolver 4 video imaging products 08/9/2000Clds.48908-j the filtered image data is output on the data output bus (dout 19-0 ). this bus is registered with three-state drivers to facilatate use on a standard microprocessor system bus. data input image data is input to the 3 x 3 convolver using din 7-0 . data present on din 7-0 is latched into a program- mable pipeline delay on the rising edge of clk. the programmable pipeline delay (1 to 4 clock cycles) allows for synchronization of input data when multiple lf48908s are cascaded together to perform larger convolutions. this delay is pro- gramed via the initialization register (see table 3). the image data format, unsigned or twos complement, is also controlled by this register. coefficient data is input to the 3 x 3 convolver using either of two coef- ficient registers (creg 0 or creg 1 ). the coefficient registers are loaded through cin 7-0 using the a 2-0 , cs, and ld controls. the coefficient data format, unsigned or twos comple- ment, is determined by the initializa- tion register. arithmetic logic unit the input data path alu with shifter allows pixel point operations to be performed on the incoming image. these operations include arithmetic functions, logical masking, and left/ right shifts. the 10-bit alu micro- code register controls the various operations. the three upper bits control the shift amount and direction while the seven lower bits determine the arithmetic or logical operation. the shift operation is performed on the output of the alu. this shift operation is independent of the arithmetic or logical operation of the alu. tables 1 and 2 show the operations of the alu microcode register. the a operand comes from the din input data path, while the b operand is taken from the alu register. the alu register is loaded using cin 7-0 and ealu. with ealu high, data from cin 7-0 is loaded into the alu register on the rising edge of clk. with ealu low, the data is held in the alu register. since cin 7-0 is also used to load the control logic regis- ters, it is possible to overwrite data in those registers if cs and ld are active when loading the alu register. therefore, special care must be taken to ensure that cs and ld are not active when writing to the alu register. programmable row buffers the two internal row buffers provide the delay needed to perform the two- dimensional convolution. the row buffers function like 8-bit serial shift registers with a user-programmable delay from 1 to 1024 stages (it is possible to select delay stages of 1 or 2, but this leads to meaningless results for a 3 x 3 kernel convolution). the row buffer length is set via the row length register (see row length register section). the row buffers are connected in series to provide the proper pixel information to the multiplier array. the cascade output (caso 7-0 ) provides a 2x row delay of the input data allowing for cascading of lf48908s to handle larger frames and/or kernel sizes. if more than 1024 delay stages are needed, it is possible to use external row buffers and bypass the internal row buffers. bit 0 of the initialization register determines if internal or external row buffers are used. if bit 0 is a 0, the internal row buffers are used. if bit 0 is a 1, the internal row buffers are bypassed and external row buffers may be used. 3 x 3 multiplier array the multiplier array comprises nine 8 x 8-bit multipliers. the active coefficient register supplies the coefficents to each of the multipliers, while the pixel data comes from the data input path and row buffers. the array forms a sum-of-products result as defined by the equation listed in figure 3. control logic four sets of registers, the alu micro- code, row length, initialization, and coefficient, define the control logic section. these registers are updated f igure 3. m ultiplier a rray o utput p1 p2 p3 p4 p5 p6 p7 p8 p9 abc def gh i pixel input data filter kernel multiplier array output a(p1) = + d(p4) + g(p7) + + + b(p2) e(p5) h(p8) + + + c(p3) f(p6) i(p9)
devices incorporated 5 lf48908 two dimensional convolver 1 2 3 4 5 6 7 8 9 10 11 08/9/2000Clds.48908-j video imaging products row length register the value stored in the row length register determines the number of delay stages for each row buffer. the number of delay stages should be set equal to the row length of the input image. the row length register may be loaded with the values 0 through 1023 (0 represents 1024 delay stages). it is possible to program the row buffers to have 1 or 2 delay stages, but this will lead to meaningless results for a 3 x 3 convolution. this register is loaded through cin 9-0 using the a 2-0 , cs, and ld controls. once the row length register has been loaded, a new value can not be loaded until the lf48908 has been reset. this is done by asserting reset. after reset goes high, the row length register must be loaded within 1024 clk cycles. if the row length register is not loaded within 1024 clk cycles, the register will automatically be loaded with a 0. initialization register the initialization register configures various functions of the device including: input data delay, input data format, coefficent data format, output rounding, cascade mode, and cascade input shift (see table 3). this register is loaded through cin 8-0 using the a 2-0 , cs, and ld controls. coefficient registers - creg 0 , creg 1 the coefficient registers are used to store the filter coefficients for the multiplier array. each coefficient through the cin bus using a 2-0 , cs, and ld (see figure 4). all the control logic registers are set to their default values when reset is active. frame does not affect the values in these registers. alu microcode register operation of the alu and shifter are determined by the value stored in the alu microcode register. this 10-bit instruction word is divided into two fields. the lower seven bits define the arithmetic and logical operations of the alu. the upper three bits specify shift distance and direction. tables 1 and 2 detail the various instruction words. this register is loaded through cin 9-0 using the a 2-0 , cs, and ld controls. also see arithmetic logic unit section. f igure 4. lf48908 c ontrol l ogic b lock d iagram a 2-0 ld cs address decode 3 encr 1 encr 0 cas cr 1 cr 0 lmc eor cin 9-0 10 alu microcode register lmc alu microcode 10 row length register eor row length 10 initialization register cas initialization data 9 8-0 i 0 h 0 g 0 f 0 e 0 d 0 c 0 b 0 a 0 cr 0 cr 1 s r q q oe oe oe oe oe oe oe oe oe i 1 h 1 g 1 f 1 e 1 d 1 c 1 b 1 a 1 oe oe oe oe oe oe oe oe oe encr 1 encr 0 i h g f e d c b a 8 8 8 8 8 8 8 8 8 coefficient register 0 coefficient register 1 9 7-0 8 7-0 8
devices incorporated lf48908 two dimensional convolver 6 video imaging products 08/9/2000Clds.48908-j loaded is determined by the data on a 2-0 during the load operation. if creg 0 is to be loaded, 010 must be placed on a 2-0 during the load opera- tion. if creg 1 is to be loaded, 011 must be placed on a 2-0 . if desired, the coefficient register that is not being used to send data to the multiplier array can be loaded with coefficient data while the lf48908 is in active operation. address decoder the address decoder is used to load the control logic registers and to determine which coefficient register sends data to the multiplier array. to load a control logic register, the address of the register must be placed on a 2-0 , the data to be written must be placed on the cin bus, and cs and ld must be asserted. the data is t able 2. alu l ogical and a rithmetic o perations t able 1. alu s hift o perations alu microcode register register bit 9 8 7 operation 0 0 0 no shift (default) 0 0 1 shift right 1 0 1 0 shift right 2 0 1 1 shift right 3 1 0 0 shift left 1 1 0 1 shift left 2 1 1 0 shift left 3 1 1 1 not valid register can hold nine 8-bit values. this allows two different 3 x 3 filter kernels to be stored simultaneously on the lf48908. the outputs of creg 0 and creg 1 are connected to the coefficient inputs of the multiplier array (a through i). the register used to supply the coefficient data is determined by the address written to the address decoder. if a 101 is written to the address decoder, creg 0 will provide the coefficient data. if a 110 is written to the address decoder, creg 1 will be used. it is possible to switch between the two coefficient registers in real time. this facilitates adaptive filtering operations. it is important to remem- ber to meet the t lcs timing specifica- tion when switching the coefficient registers. when a coefficient register is selected to supply data to the multiplier array (one of the registers is always selected), all of its outputs are enabled simultaneously. when reset is asserted, creg 0 is the default register selected to supply the coeffi- cient data. creg 0 and creg 1 are loaded through cin 7-0 using the a 2-0 , cs, and ld controls. the nine coefficient values are presented on cin 7-0 one by one, in order from a to i. as each value is placed on cin 7-0 , it is latched into the selected coefficient register using cs and ld. the register to be latched into the addressed register when ld goes high. to select a coefficient register (creg 0 or creg 1 ) to send data to the multiplier array, the appropriate address must be placed on a 2-0 , and cs and ld must be asserted. when ld goes high, the addressed register will begin supply- ing coefficient data to the multiplier array. table 4 lists all of the register addresses. the control logic registers can be modified during active operation of the lf48908. if this is done, it is very important to meet the t lcs timing specification. this is to ensure that the outputs of the control logic registers have enough time to change before the next rising edge of clk. if t lcs is not met, unexpected results may occur on dout 19-0 for one clock cycle. there are two situations in which t lcs may alu microcode register register bit 6 5 4 3 2 1 0 operation 0 0 0 0 0 0 0 logical (00000000) 1 1 1 1 0 0 0 logical (11111111) 0 0 1 1 0 0 0 logical (a) (default) 0 1 0 1 0 0 0 logical (b) 1 1 0 0 0 0 0 logical (a) 1 0 1 0 0 0 0 logical (b) 0 1 1 0 0 0 1 arithmetic (a + b) 1 0 0 1 0 1 0 arithmetic (a C b) 1 0 0 1 1 0 0 arithmetic (b C a) 0 0 0 1 0 0 0 logical (a and b) 0 0 1 0 0 0 0 logical (a and b) 0 1 0 0 0 0 0 logical (a and b) 0 1 1 1 0 0 0 logical (a or b) 1 0 1 1 0 0 0 logical (a or b) 1 1 0 1 0 0 0 logical (a or b) 1 1 1 0 0 0 0 logical (a nand b) 1 0 0 0 0 0 0 logical (a nor b) 0 1 1 0 0 0 0 logical (a xor b) 1 0 0 1 0 0 0 logical (a xnor b)
devices incorporated 7 lf48908 two dimensional convolver 1 2 3 4 5 6 7 8 9 10 11 08/9/2000Clds.48908-j video imaging products be ignored. if the lf48908 is not in active operation or if the innactive coefficient register is being written to during active operation. cascade operation the cascade input lines (casi 15-0 ) and cascade output lines (caso 7-0 ) are used to allow convolutions of kernel sizes larger than 3 x 3. the cascade input lines are also used to allow convolutions on row lengths longer than 1024 pixels. the cascade mode bit (bit 0) of the initialization register determines the function of the cascade input lines. if the cas- cade mode bit is a 0, then the cascade input lines are to be used to cascade multiple lf48908s together to perform convolutions of larger kernel sizes. casi 15-0 will be left shifted (by an amount determined by bits 7 and 8 of the initialization register) and then added to dout 19-0 . cascading is accomplished by connecting caso 7-0 and dout 19-0 of one lf48908 to din 7-0 and casi 15-0 respectively of another lf48908. if the cascade mode bit is a 1, then the cascade input lines are to be used with exter- nal row buffers to allow for longer row lengths. in this mode, the cas- cade input lines are split into two 8-bit data busses (casi 15-8 and casi 7-0 ) which are fed directly into the multi- plier array. t able 3. i nitialization r egister bit function 0 cascade mode 0 multiplier input from internal row buffers 1 multiplier input from external buffers 2 1 input data delay 0 0 no data delay registers used 0 1 one data delay register used 1 0 two data delay registers used 1 1 three data delay registers used 3 input data format 0 unsigned integer format 1 twos complement format 4 coefficient data format 0 unsigned integer format 1 twos complement format 6 5 output rounding 0 0 no rounding 0 1 round to 16 bits (i.e. dout19-4) 1 0 round to 8 bits (i.e. dout19-12) 1 1 not valid 8 7 casi15-0 input shift 0 0 no shift 0 1 shift casi15-0 left two 1 0 shift casi15-0 left four 1 1 shift casi15-0 left eight a 2-0 function 000 load row buffer length register 001 load alu microcode register 010 load coefficient register 0 011 load coefficient register 1 100 load initialization register 101 select coefficient register 0 for internal processing 110 select coefficient register 1 for internal processing 111 no operation t able 4. c ontrol l ogic a ddress m ap
devices incorporated lf48908 two dimensional convolver 8 video imaging products 08/9/2000Clds.48908-j symbol parameter test condition min typ max unit v oh output high voltage v cc = min., i oh = C400 a 2.8 v v ol output low voltage v cc = min., i ol = 2.0 ma 0.4 v v ih input high voltage 2.0 v cc v v il input low voltage (note 3) 0.0 0.8 v i ix input current ground v in v cc (note 12) 10 a i oz output leakage current ground v out v cc (note 12) 10 a i cc1 v cc current, dynamic (notes 5, 6) 110 ma i cc2 v cc current, quiescent (note 7) 500 a c in input capacitance t a = 25c, f = 1 mhz 10 pf c out output capacitance t a = 25c, f = 1 mhz 12 pf o perating c onditions to meet specified electrical and switching characteristics e lectrical c haracteristics over operating conditions (note 4) mode temperature range (ambient) supply voltage active operation, commercial 0c to +70c 4.75 v v cc 5.25 v active operation, military C55c to +125c 4.50 v v cc 5.50 v storage temperature ........................................................................................................... C65c to +150c operating ambient temperature ........................................................................................... C55c to +125c v cc supply voltage with respect to ground ............................................................................ C0.5 v to +7. 0v input signal with respect to ground ............................................................................... C0.5 v to v cc + 0.5 v signal applied to high impedance output ...................................................................... C0.5 v to v cc + 0.5 v output current into low outputs ................................................................................................ ............. 25 ma latchup current ................................................................................................................ ............... > 400 ma m aximum r atings above which useful life may be impaired (notes 1, 2, 3, 8)
devices incorporated 9 lf48908 two dimensional convolver 1 2 3 4 5 6 7 8 9 10 11 08/9/2000Clds.48908-j video imaging products lf48908C 50 31 25 symbol parameter min max min max min max t cyc cycle time 50 31 25 t pwh clock pulse width high 20 12 8 t pwl clock pulse width low 20 13 8 t ds data input setup time 14 13 8 t dh data input hold time 0 0 0 t cs cin 7-0 setup time 16 14 10 t ch cin 7-0 hold time 0 0 0 t es ealu setup time 14 12 10 t eh ealu hold time 0 0 0 t d output delay 22 16 15 t ena three-state output enable delay (note 11) 22 16 15 t dis three-state output disable delay (note 11) 32 28 8 c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) switching characteristics s witching w aveforms :c onvolver d ata i/o clk t cyc t pwl t pwh din 7-0 casi 15-0 t ds t dh dout 19-0 caso 7-0 t d cin 7-0 t cs t ch ealu t es t eh (alu reg data) oe t d t dis t ena high impedance
devices incorporated lf48908 two dimensional convolver 10 video imaging products 08/9/2000Clds.48908-j 12345678901234567890123456789012123456789012345 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 1 234567890123456789012345678901212345678901234 5 12345678901234567890123456789012123456789012345 lf48908C 50 * 37 * 25 * symbol parameter min max min max min max t cyc cycle time 50 37 25 t pwh clock pulse width high 20 15 8 t pwl clock pulse width low 20 15 8 t ds data input setup time 17 16 8 t dh data input hold time 0 0 0 t cs cin 7-0 setup time 20 17 10 t ch cin 7-0 hold time 0 0 0 t es ealu setup time 17 15 10 t eh ealu hold time 0 0 0 t d output delay 28 19 15 t ena three-state output enable delay (note 11) 28 19 15 t dis three-state output disable delay (note 11) 40 35 8 m ilitary o perating r ange (C55c to +125c) notes 9, 10 (ns) s witching w aveforms :c onvolver d ata i/o clk t cyc t pwl t pwh din 7-0 casi 15-0 t ds t dh dout 19-0 caso 7-0 t d cin 7-0 t cs t ch ealu t es t eh (alu reg data) oe t d t dis t ena high impedance 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *d iscontinued s peed g rade
devices incorporated 11 lf48908 two dimensional convolver 1 2 3 4 5 6 7 8 9 10 11 08/9/2000Clds.48908-j video imaging products 1234567890123456789012345678901212345678901234 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1234567890123456789012345678901212345678901234 c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) lf48908C 50 * 37 * 25 * symbol parameter min max min max min max t lpw ld pulse width 20 15 8 t lcs ld setup time (applies only during active operation) 37 30 15 t cds configuration data setup time 20 17 10 t cdh configuration data hold time 0 0 0 t as address setup time 15 15 10 t ah address hold time 0 0 0 t css cs setup time 0 0 0 t csh cs hold time 0 0 0 m ilitary o perating r ange (C55c to +125c) notes 9, 10 (ns) s witching w aveforms :c onfiguration d ata ld cs a 2-0 cin 9-0 t cds t cdh t css t lpw t csh t as t ah clk t lcs * *applies only when the lf48908 is in active operation. lf48908C 50 31 25 symbol parameter min max min max min max t lpw ld pulse width 20 12 8 t lcs ld setup time (applies only during active operation) 30 25 15 t cds configuration data setup time 16 14 10 t cdh configuration data hold time 0 0 0 t as address setup time 13 13 10 t ah address hold time 0 0 0 t css cs setup time 0 0 0 t csh cs hold time 0 0 0 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *d iscontinued s peed g rade
devices incorporated lf48908 two dimensional convolver 12 video imaging products 08/9/2000Clds.48908-j 1234567890123456789012345678901212345678901234 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1234567890123456789012345678901212345678901234 lf48908C 50 * 37 * 25 * symbol parameter min max min max min max t hs hold setup time 14 13 9 t hh hold hold time 2 2 0 t fpw frame pulse width 50 37 8 t fs frame setup time 30 25 20 t rpw reset pulse width 50 37 8 lf48908C 50 31 25 symbol parameter min max min max min max t hs hold setup time 12 11 9 t hh hold hold time 1 1 0 t fpw frame pulse width 50 31 8 t fs frame setup time 25 21 20 t rpw reset pulse width 50 31 8 c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) m ilitary o perating r ange (C55c to +125c) notes 9, 10 (ns) s witching w aveforms :c ontrol s ignals clk hold t hs t hh reset t rpw frame t hs t fpw t fs 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *d iscontinued s peed g rade
devices incorporated 13 lf48908 two dimensional convolver 1 2 3 4 5 6 7 8 9 10 11 08/9/2000Clds.48908-j video imaging products 1. maximum ratings indicate stress specifications only. functional oper- ation of these products at values beyond those indicated in the operating condi- tions table is not implied. exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. the products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this device provides hard clamping of transient undershoot and overshoot. in- put levels below ground or above v cc will be clamped beginning at C0.6 v and v cc + 0.6 v. the device can withstand indefinite operation with inputs in the range of C0.5 v to +7.0 v. device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 ma. 4. actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. supply current for a given applica- tion can be accurately approximated by: where n = total number of device outputs c = capacitive load per output v = supply voltage f = clock frequency 6. tested with all outputs changing ev- ery cycle and no load, at a 20 mhz clock rate. 7. tested with all inputs within 0.1 v of v cc or ground, no load. 8. these parameters are guaranteed but not 100% tested. ncv f 4 2 notes 9. ac specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 v (except t dis test), and input levels of nominally 0 to 3.0 v. output loading may be a resistive divider which provides for specified i oh and i ol at an output voltage of v oh min and v ol max respectively. alternatively, a diode bridge with upper and lower current sources of i oh and i ol respectively, and a balancing voltage of 1.5 v may be used. parasitic capacitance is 30 pf minimum, and may be distributed. this device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. as a result, care must be exercised in the testing of this device. the following measures are recommended: a. a 0.1 f ceramic capacitor should be installed between v cc and ground leads as close to the device under test (dut) as possible. similar capacitors should be installed between device v cc and the tester common, and device ground and tester common. b. ground and v cc supply planes must be brought directly to the dut socket or contactor fingers. c. input voltages should be adjusted to compensate for inductive ground and v cc noise to maintain required dut input levels relative to the dut ground pin. 10. each parameter is shown as a min- imum or maximum value. input re- quirements are specified from the point of view of the external system driving the chip. setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. responses from the internal circuitry are specified from the point of view of the device. output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. for the t ena test, the transition is measured to the 1.5 v crossing point with datasheet loads. for the t dis test, the transition is measured to the 200mv level from the measured steady-state output voltage with 10ma loads. the balancing volt- age, v th , is set at 3.5 v for z-to-0 and 0-to-z tests, and set at 0 v for z- to-1 and 1-to-z tests. 12. these parameters are only tested at the high temperature extreme, which is the worst case for leakage current. s1 i oh i ol v th c l dut oe 0.2 v t dis t ena 0.2 v 1.5 v 1.5 v 3.5v vth 1 z 0 z z 1 z 0 1.5 v 1.5 v 0v vth v ol * v oh * v ol * v oh * measured v ol with i oh = C10ma and i ol = 10ma measured v oh with i oh = C10ma and i ol = 10ma f igure b. t hreshold l evels f igure a. o utput l oading c ircuit
devices incorporated lf48908 two dimensional convolver 14 video imaging products 08/9/2000Clds.48908-j plastic j-lead chip carrier (j3) lf48908jc50 LF48908JC31 lf48908jc25 ordering information 0c to +70c c ommercial s creening speed 50 ns 31 ns 25 ns 84-pin 1 2 3 4 5 6 7 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 84 83 82 81 80 79 44 43 45 46 47 49 38 37 39 40 41 42 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 top view 8 9 10 11 78 77 76 75 36 35 34 33 50 51 52 53 cin 3 cin 4 cin 5 cin 6 cin 7 cin 8 cin 9 gnd clk v cc hold ld cs a 2 a 1 a 0 ealu casi 15 casi 14 casi 13 casi 12 caso 6 caso 7 dout 0 dout 1 dout 2 gnd dout 3 dout 4 dout 5 dout 6 dout 7 v cc dout 8 gnd dout 9 dout 10 dout 11 dout 12 dout 13 dout 14 gnd casi 11 casi 10 casi 9 casi 8 casi 7 casi 6 casi 5 casi 4 casi 3 v cc casi 2 casi 1 casi 0 frame reset gnd dout 19 dout 18 dout 17 dout 16 dout 15 cin 2 cin 1 cin 0 din 7 din 6 din 5 din 4 din 3 din 2 din 1 din 0 v cc oe gnd caso 0 caso 1 caso 2 caso 3 caso 4 gnd caso 5 C40c to +85c c ommercial s creening
devices incorporated 15 lf48908 two dimensional convolver 1 2 3 4 5 6 7 8 9 10 11 08/9/2000Clds.48908-j video imaging products plastic quad flatpack (q2) lf48908qc31 lf48908qc25 ordering information 0c to +70c c ommercial s creening speed 31 ns 25 ns 100-pin cin 1 cin 2 nc nc cin 3 cin 4 cin 5 cin 6 cin 7 cin 8 cin 9 gnd gnd clk v cc v cc hold ld cs a 2 a 1 a 0 ealu casi 15 casi 14 casi 13 casi 12 nc nc casi 11 cin 0 din 7 din 6 din 5 din 6 din 3 din 2 din 1 din 0 v cc v cc oe gnd gnd caso 0 caso 1 caso 2 caso 3 caso 4 gnd gnd caso 5 nc caso 6 caso 7 dout 0 dout 1 dout 2 gnd gnd dout 3 dout 4 dout 5 dout 6 dout 7 vcc vcc dout 8 gnd gnd dout 9 dout 10 dout 11 dout 12 dout 13 dout 14 gnd gnd dout 15 dout 16 casi 10 casi 9 casi 8 casi 7 casi 6 casi 5 casi 4 casi 3 v cc v cc casi 2 casi 1 casi 0 frame reset gnd gnd dout 19 dout 18 dout 17 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 C40c to +85c c ommercial s creening
devices incorporated lf48908 two dimensional convolver 16 video imaging products 08/9/2000Clds.48908-j 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 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1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 ceramic pin grid array (g6) ordering information 0c to +70c c ommercial s creening speed C55c to +125c mil-std-883 c ompliant C55c to +125c c ommercial s creening 84-pin a b c d e f g h j k l top view through package (i.e., component side pinout) 12345 6 7 8 9 10 11 cin 0 cin 3 cin 4 cin 7 gnd v cc a 2 ealu casi 13 casi 11 casi 9 din 7 cin 1 cin 9 hold ld casi 10 casi 8 din 5 din 6 casi 7 casi 6 din 2 din 3 din 4 casi 5 casi 4 casi 3 din 1 caso 0 din 0 casi 2 v cc reset oe gnd v cc casi 1 frame casi 0 caso 1 caso 2 dout 19 gnd cin 2 cin 5 cin 6 cin 8 clk a 1 cs a 0 casi 15 casi 14 casi 12 caso 3 gnd dout 3 dout 7 v cc dout 16 dout 18 caso 4 caso 5 caso 7 dout 2 dout 4 dout 9 gnd dout 11 dout 14 gnd dout 17 caso 6 dout 0 dout 1 gnd dout 5 dout 6 dout 8 dout 10 dout 12 dout 13 dout 15 discontinued package

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